Control Unit in Computer Architecture – Complete BCA Notes

Hey students and tech pros! Have you ever wondered what makes a CPU function smoothly? The Control Unit (CU) is the boss that keeps everything running smoothly. These notes break down the Control Unit from basics to advanced designs – perfect for BCA exams, interviews, or quick revision.

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What is a Control Unit? 

Think of the Control Unit as the traffic policeman inside your computer's CPU. It directs data flow, tells the ALU what to calculate, and ensures instructions execute in the right order. Without it, the CPU would be chaos!

Key Role:

• Fetches instructions from memory

• Decodes what they mean

• Generates control signals to execute them

• Manages the entire instruction cycle

Where it fits in CPU: ALU does maths, CU does management. Together, they form the CPU brain.

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Registers in Instruction Cycle

Every instruction goes through stages, and specific registers help manage data movement. Here's the core team:

• Program Counter (PC): Holds address of next instruction

• Memory Address Register (MAR): Gets PC value, fetches from memory

• Memory Buffer Register (MBR): Holds fetched instruction/data

• Instruction Register (IR): Stores current instruction for decoding

• Accumulator (AC): Holds ALU results

• Status Register: Tracks flags (zero, carry, overflow)

Example: PC = 100 → MAR loads 100 → MBR gets instruction → IR decodes it.

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Micro-Operations in Sub-Cycles

Micro-operations are tiny steps (like "load register" or "add bits") that build full instructions. Each cycle breaks into these:

Fetch Cycle Micro-Ops:

• PC → MAR

• Read memory → MBR

• MBR → IR

• PC + 1 → PC

Execute Cycle Micro-Ops (for ADD):

• IR operand → MAR

• Memory → AC

• AC + operand → AC

Layman Analogy: Like recipe steps – fetch ingredients (Fetch), mix (Execute), serve (Store).

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The Fetch Cycle (Step-by-Step)

Purpose: Grab next instruction from memory. Happens every time!

Micro-Operations:

1. PC out → MAR (address to memory)

2. Read memory → MBR (fetch instruction)

3. MBR out → IR (load for decoding)

4. PC out + 1 → PC (point to next)

Timing: Controlled by clock pulses – one cycle per instruction start.
Example: Fetching ADD 200 from address 100.

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The Indirect Cycle

When needed: If instruction uses indirect addressing (operand at another address).

Micro-Ops:

1. IR address → MAR

2. Memory → IR (get actual address)

3. Ready for Execute cycle

Use Case: Pointers in programs – LOAD [R1] where R1 holds real address.
Why extra cycle? Saves instruction space but adds time.

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The Execute Cycle

The main action! Performs what instruction demands.

For Arithmetic (ADD R1, R2):

• R1 → ALU input

• R2 → ALU input

• ALU add → AC

• Update status flags

For Branch (JMP 300):

• 300 → PC (jump to new address)

Variable Length: Depends on instruction complexity – simple ops = few micro-ops.

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The Interrupt Cycle

Emergency brake! Handles external events (keyboard press, timer).

Steps:

1. Save current PC and status (to stack)

2. Load interrupt handler address → PC

3. Execute handler

4. Restore PC (return)

Types: Hardware (printer done), Software (division by zero).
Priority: Maskable (can ignore) vs Non-maskable (must handle).

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CPU Responsibilities & Requirements

Core Jobs of CPU:

• Execute instructions sequentially

• Handle interrupts promptly

• Manage registers and memory

• Perform ALU operations

Functional Needs:

• Fetch capability (memory access)

• Decode logic (instruction interpreter)

• Control signals (to ALU, registers)

• Timing circuits (synchronise everything)

Block Diagram Signals:

• Read/Write to memory

• ALU select (add/sub/etc.)

• Register load/enable

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Control Unit Structure & Signals

Inputs to CU:

• Instruction (from IR)

• Status flags (zero, carry)

• Clock pulses

• Interrupt signals

Outputs (Control Signals):

• To ALU: Operation select

• To Registers: Load, clear

• To Memory: Read/write

• Buses: Enable data flow

Design Goal: Generate exact signal sequence for every instruction.

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Types of Control Unit Designs

Two main approaches: Hardwired (fixed circuits) vs Micro-programmed (software-like control).

Feature	Hardwired CU	Micro-programmed CU
Speed	Super fast (wires + gates)	Slower (memory lookup)
Flexibility	Hard to change	Easy to modify (change microcode)
Cost	Complex, expensive hardware	Cheaper, uses ROM
Best For	Simple CPUs	Complex, modern processors

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Hardwired Control Unit (Deep Dive)

How it Works: Pure logic gates and circuits – no memory. Instruction bits + flags → direct control signals.

Two Main Issues:

1. Complexity Explosion: More instructions = exponentially more gates.

2. Unchangeable: Fix a bug? Rewire hardware!

Control Unit Logic:

Inputs: Opcode (6 bits) + Flags (4 bits) = 2^10 combinations
Outputs: 20+ control signals
Uses: Decoders, multiplexers, counters
  

Example: Opcode 0010 (ADD) → Gates fire "ALU_ADD + AC_LOAD".

Pros: Lightning speed. Cons: Rigid.

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Micro-Programmed Control Unit

Smart Alternative: Control logic stored as micro-instructions in a Control Memory (ROM).

How it Works:

1. Fetch micro-instruction using micro-PC

2. Execute its control fields

3. Next address from micro-instruction

4. Repeat till full instruction done

Benefits: Change ROM content = new CPU behaviour. Used in Intel x86!

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Micro-Instruction Formats

Micro-instructions control tiny steps. Two styles:

Horizontal Micro-Instruction Format

• Wide, parallel fields (one bit per control signal)

• All signals activate simultaneously

• Fast execution

Structure:

| Opcode | ALU | Reg1 | Reg2 | Memory | Next Addr |
 

Example: 64-bit wide – each bit controls one signal directly.

Vertical Micro-Instruction Format

• Compact, encoded fields (like mini opcodes)

• Decoder expands to signals

• Memory efficient

Structure:

| Micro-Opcode | Source | Dest | Op | Branch |
 

Example: "LOAD_AC" field decodes to multiple signals.

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Horizontal vs Vertical Format

Aspect	Horizontal	Vertical
Width	Wide (50-100 bits)	Narrow (20-40 bits)
Speed	Faster (no decode)	Slower (decode needed)
Flexibility	Less (fixed fields)	More (encoded)
Memory Use	High	Low
Best For	High-speed RISC	Memory-limited systems

Rule: Horizontal = speed demon, Vertical = space saver.

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Microinstruction Sequencing Techniques

How to chain micro-instructions:

Two Address Field Microinstruction

| Control Fields | Addr1 | Addr2 |
 

• Match current micro-PC with Addr1 → Jump to Addr2

Single Address Field Microinstruction

| Control Fields | Next Addr |
 

• Always jump to specified address

Variable Format Microinstruction

• Flexible length – short for simple ops, long for complex

• Saves memory, uses prefix/suffix encoding

Techniques Compared:

• Unconditional: Always next sequential

• Conditional: Branch on flags

• Jump: Direct to subroutine-like addresses

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Key Takeaways – Quick Revision

• Control Unit = CPU Director – manages fetch, execute, interrupts

• Hardwired CU = Fast but rigid (gates only)

• Micro-programmed CU = Flexible, ROM-based (modern choice)

• Instruction Cycles: Fetch → Indirect? → Execute → Interrupt?

• Micro-instructions power detailed control – horizontal (speed) vs vertical (compact)

• Pro Tip: x86 processors use microcode for backward compatibility!

Exam Gold: Draw CU block diagram + compare Hardwired vs Microprogrammed table = full marks.

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