Unit 3: Control Unit

Control Unit (CU)

The Control Unit (CU) is a vital part of the CPU. It does not perform calculations, but it controls and coordinates all activities of the computer system.

Main functions of CU:

• Fetches instructions from memory
• Decodes instructions
• Generates control signals
• Directs data flow between CPU, memory, and I/O devices

Instruction Types

Instructions are classified based on the type of operation they perform.

Data Transfer Instructions

Used to move data between registers, memory, and I/O.

Examples:

• MOV
• LOAD
• STORE

Arithmetic Instructions

Used to perform mathematical operations.

Examples:

• ADD
• SUB
• MUL
• DIV

Logical Instructions

Used for bit-wise logical operations.

Examples:

• AND
• OR
• NOT
• XOR

Control (Branch) Instructions

Used to change the sequence of execution.

Examples:

• JUMP
• CALL
• RETURN
• BRANCH

Input / Output Instructions

Used for data exchange with I/O devices.

Examples:

• IN
• OUT

Instruction Formats

An instruction format defines the layout of bits in an instruction. It specifies:

• Operation to be performed
• Location of operands

Common Fields in an Instruction

1. Opcode Field - Specifies the operation (ADD, SUB, etc.)
2. Operand Field - Specifies registers or memory addresses
3. Addressing Mode Field - Specifies how operand is accessed

Types of Instruction Formats

(a) Zero-Address Instruction—Used in stack organization. Example: ADD

(b) One-Address Instruction - One operand is explicitly mentioned. Example: ADD A

(c) Two-Address Instruction - Two operands specified. Example: ADD R1, R2

(d) Three-Address Instruction - Two source operands and one destination. Example: ADD R1, R2, R3

Comparison of Instruction Formats

Format	No. of Addresses	Used In
Zero	0	Stack
One	1	Accumulator
Two	2	General register
Three	3	RISC processors

Instruction Cycle

The instruction cycle is the sequence of steps performed by the CPU to execute one instruction.

Phases of Instruction Cycle

1. Fetch Cycle
2. Decode Cycle
3. Execute Cycle
4. Interrupt Cycle (if any)

Instruction Sub-Cycles

5.1 Fetch Cycle

Steps:

1. Program Counter (PC) holds address of next instruction
2. Instruction is fetched from memory
3. Instruction is stored in Instruction Register (IR)
4. PC is incremented

Micro-operations:

MAR ← PC  
MDR ← Memory[MAR]  
IR ← MDR  
PC ← PC + 1

Decode Cycle

• Control Unit decodes opcode

Determines:

• Type of instruction
• Addressing mode
• Required micro-operations

Execute Cycle

• Actual operation is performed
• Depends on instruction type

Examples:

• Arithmetic operation
• Memory access
• Branch operation

Interrupt Cycle (Optional)

• Occurs if interrupt is detected
• CPU saves current state
• Control is transferred to interrupt service routine

Micro-Operations

A micro-operation is the smallest operation performed on data stored in registers.

Types:

1. Register Transfer Micro-operations
2. Arithmetic Micro-operations
3. Logic Micro-operations
4. Shift Micro-operations

Examples of Micro-Operations

Type	Example
Register transfer	R1 ← R2
Arithmetic	R1 ← R2 + R3
Logic	R1 ← R2 AND R3
Shift	R1 ← R1 << 1

Execution of a Complete Instruction

Example:

Instruction:

ADD R1, R2

Step-by-Step Execution:

Fetch Cycle

MAR ← PC  
MDR ← Memory[MAR]  
IR ← MDR  
PC ← PC + 1

Decode Cycle

• CU decodes opcode as ADD
• Identifies R1 and R2

Execute Cycle

R1 ← R1 + R2

Write Back

• Result stored in R1
• Flags updated

Hardwired vs Microprogrammed Control Unit

Hardwired Control Unit

• Uses logic gates
• Very fast
• Difficult to modify

Microprogrammed Control Unit

• Uses control memory
• Easy to modify
• Slower than hardwired

Summary Table

Topic	Key Point
Control Unit	Controls CPU operations
Instruction Types	Data, Arithmetic, Logic, Control
Instruction Format	Defines instruction layout
Instruction Cycle	Fetch → Decode → Execute
Micro-operations	Small register-level actions

Conclusion

The Control Unit ensures smooth execution of programs by managing instruction flow and generating control signals.
Understanding instruction formats, cycles, micro-operations, and execution steps is essential for mastering computer organization and architecture.

Program Control

Program control refers to the way a processor controls the sequence of instruction execution in a program.
Normally, instructions are executed sequentially, but program control instructions can change this flow.

Types of Program Control Instructions

(a) Branch Instructions

• Change the normal flow of execution
• Can be conditional or unconditional

Examples:

• JUMP
• BRANCH IF ZERO

(b) Loop Control Instructions

• Used for repetition of instructions

Examples:

• FOR, WHILE (at machine level using branch instructions)

(c) Subroutine Control Instructions

• Used for function or procedure calls

Examples:

• CALL
• RETURN

(d) Interrupt Control

• Temporarily halts normal execution
• Transfers control to interrupt service routine

Program Status Word (PSW)

• Stores condition flags (Zero, Carry, Sign, Overflow)
• Helps in decision-making during program control

Reduced Instruction Set Computer (RISC)

RISC (Reduced Instruction Set Computer) is a processor design philosophy that uses:

• A small number of simple instructions
• Uniform instruction formats
• High execution speed

Key Features of RISC

• Simple instructions
• One instruction executed per clock cycle (ideal case)
• Load/store architecture
• Large number of registers
• Few addressing modes

Advantages of RISC

• Faster execution
• Easy pipelining
• Simple control unit
• Reduced hardware complexity

Disadvantages of RISC

• Larger program size
• More instructions required
• Heavy dependence on compiler optimization

RISC vs CISC Comparison

Feature	RISC	CISC
Instruction set	Small	Large
Instruction length	Fixed	Variable
Execution	Fast	Slower
Pipelining	Easy	Difficult
Control unit	Hardwired	Microprogrammed

Pipelining

Pipelining is a technique where multiple instructions are overlapped in execution, similar to an assembly line.

Goal:

• Increase instruction throughput
• Improve CPU performance

Pipeline Stages

A typical instruction pipeline has 5 stages:

1. IF – Instruction Fetch
2. ID – Instruction Decode
3. EX – Execute
4. MEM – Memory Access
5. WB – Write Back

Advantages of Pipelining

• Increased throughput
• Better utilization of hardware
• Faster instruction execution

Pipeline Hazards

(a) Structural Hazards - Two instructions need the same resource

(b) Data Hazards - One instruction depends on result of previous instruction

(c) Control Hazards - Caused by branch instructions

Solutions to Pipeline Hazards

• Forwarding
• Pipeline stalling
• Branch prediction
• Delayed branching

Hardwired Control Unit

A hardwired control unit uses logic gates, flip-flops, and decoders to generate control signals.

Characteristics

• Fixed control logic
• Very fast
• Difficult to modify

Advantages

• High speed
• Suitable for RISC processors

Disadvantages

• Complex design
• Hard to upgrade or modify

Microprogrammed Control Unit

A microprogrammed control unit generates control signals using microinstructions stored in control memory.

Microprogram

• A sequence of microinstructions
• Each microinstruction performs micro-operations

Micro-Program Sequencing

Micro-program sequencing defines how the next microinstruction is selected during execution.

Types of Sequencing

1. Sequential Sequencing - Next microinstruction follows current one
2. Branching Sequencing - Based on condition or opcode
3. Subroutine Sequencing - Used for common microinstruction routines

Horizontal and Vertical Microprogramming

Horizontal Microprogramming

• Wide microinstruction word
• Each bit directly controls a hardware unit

Features

• High parallelism
• Fast execution
• Large control memory

Example: 101011001010

Vertical Microprogramming

• Narrow microinstruction word
• Encoded control signals

Features

• Less control memory
• Slower due to decoding
• More compact

Comparison Table

Feature	Horizontal	Vertical
Control word size	Large	Small
Speed	Very high	Lower
Hardware cost	High	Low
Decoding	No	Yes
Parallelism	High	Limited

Hardwired vs Microprogrammed Control (Summary)

Feature	Hardwired	Microprogrammed
Speed	Very fast	Slower
Flexibility	Low	High
Design complexity	High	Moderate
Used in	RISC	CISC

Conclusion

• Program control manages the execution flow of instructions.
• RISC architecture improves speed and supports efficient pipelining.
• Pipelining increases instruction throughput.
• Hardwired control is fast but inflexible.
• Microprogrammed control is flexible and uses microinstructions.
• Horizontal and vertical microprogramming differ in speed, memory size, and complexity.